First, an example of a typical configuration of the memory controller will be described with reference to FIG. 3. FIG. 3 is referred to in a description of an embodiment of the present invention which will be given later as well. As shown in FIG. 3, a memory controller 20 is connected to a CPU 10 (processor) which is an upper layer device, via an address bus (ADDR), a data bus (RDATA), control signals such as a bus transfer control signal TRANS, a signal SIZE that defines a transfer unit size, and a ready signal RDY, and performs control over selection of a memory 30 through a chip select signal MCSZ, output of an address MADDR to the memory 30, reading of data MDIN from the memory 30, and writing of data to the CPU 10.
In FIG. 3, a write data bus (WDATA) between the CPU 10 and the memory controller 20, write data MDOUT from the memory controller 20 to the memory 30 are omitted. Control signals such as a write enable signal and an output enable signal from the memory controller 20 to the memory 30 are also omitted.
FIG. 4 is a timing waveform diagram for explaining an example of an operation of the memory controller in FIG. 3. The configuration shown in FIG. 3 and timing operations shown in FIG. 4 are prepared by an inventor of the present invention based on a description in Non-patent Document 1.
Referring to FIG. 4, CLK is a clock signal for driving the CPU 10 and the memory controller 20.
The RDY signal is a control signal output from the memory controller 20 to the CPU 10, and notifies completion of the bus cycle (memory access cycle) to the CPU 10. In the example in FIG. 4, the CPU 10 determines that the bus cycle is completed when the RDY signal is high (active) at a rising edge of the clock signal CLK. When the RDY signal is low (inactive) at the rising edge of the clock signal CLK, the bus cycle is extended on a clock cycle basis. Incidentally, referring to FIG. 4, the bus cycle is completed in two clock cycles, and the bus cycle extended on a clock cycle basis is not shown in each of clock cycles (1) to (11). The RDY signal in FIGS. 3 and 4 corresponds to a clock enable signal CLKEN in Non-patent Document 1. In Non-patent Document 1, a value of the signal CLKEN is sampled at a rising edge of the clock signal CLK in the CPU (core). For each clock cycle, control is performed so that when the signal CLKEN is high, the bus cycle is completed, and when the signal CLKEN is low, the bus cycle is extended.
The bus transfer control signal TRANS (also referred to as a “bus transfer state signal” or a “memory request signal”) is a control signal (of two bits) output from the CPU 10 to the memory controller 20, and notifies to the memory controller 20 following types of a bus access:                a nonsequential cycle (Nonseq; also referred to as a “nonsequential access”)        a sequential cycle (Seq; also referred to as a “sequential access”)        an internal cycle (Internal).        
Though no particular limitation is imposed, the signal TRANS is output in synchronization with a predetermined rise of the clock signal CLK at a beginning of the bus cycle.
The nonsequential cycle (NonSeq) instructs that an address that is not restricted by or unrelated to an address of an immediately preceding cycle be output as an address of a current cycle.
The sequential cycle (Seq) instructs that an address in a current cycle be the address obtained by incrementing an address in an immediately preceding cycle by a half word or a full word. The sequential cycle (Seq) is used for a burst access to a DRAM memory, for example.
The internal cycle instructs that the CPU 10 perform an internal operation and does not perform bus transfer. Referring to FIG. 4, for simplification, the CPU 10 is described to output to the memory controller 20 an address obtained by incrementing the address of an immediately preceding cycle in the sequential cycle (Seq) by one. That is, an increment unit for sequential access addresses is set to one, for the simplification.
ADDR is an address signal on an address bus which is supplied to the memory controller 20 from the CPU 10.
MADDR is an address bus signal which is supplied to the memory 30 from the memory controller 20.
MDIN is data (read data) which is output to the memory controller 20 from the memory 30.
RDATA is read data which is output onto a read data bus for the CPU 10 from the memory controller 20. In FIG. 4, MCSZ and SIZE in FIG. 3 are omitted.
As seen from FIG. 4 as well, two clock cycles are required for a bus cycle for a read access, and a wait corresponding to one clock cycle is always inserted. In a next bus cycle after one bus cycle is completed, the access from the memory controller 20 to the memory 30 is made using an address associated with the one bus cycle. More specifically, after an address is output from the CPU 10 in a certain bus cycle (refer to a clock cycle (1), (3), (5), or the like), the address MADDR from the memory controller 20 to the memory 30 is output after two clock cycles (refer to a clock cycle (3), (5), (7), or the like). Then, the data MDIN read from the memory, corresponding to the address in the immediately preceding bus cycle is output to the read data bus RDATA (refer to a clock cycle (2), (4), (6), (8), or the like).
In each bus cycle, the memory controller 20 makes the RDY signal active (HIGH level) two clocks after the read data is output to the read bus RDATA (refer to the clock cycle (2), (4), (6), (8), or the like), thereby inserting a wait cycle corresponding to one clock.
A description will be added to the timing operations shown in FIG. 4. In the clock cycle (1), a type of the bus cycle is set to the nonsequential cycle (NonSeq), and in this bus cycle, an address Aa is supplied to the memory controller 20 from the CPU 10. The address Aa is supplied to the memory 30 from the memory controller 20 in the clock cycle (3) as the address output MADDR corresponding to this address. Then, data Da is supplied to the memory controller 20 as the data MDIN from the memory 30. The memory controller 20 sets the RDY signal active (HIGH level) in synchronization with the rising edge of the clock signal CLK in the clock cycle (2). The CPU 10 receives this RDY signal (In the example shown in FIG. 4, the CPU 10 samples the RDY signal responsive to the fall of the clock signal CLK in the clock cycle (2)), and outputs the control signal TRANS and the address signal ADDR in synchronization with the falling edge of the clock in the clock cycle (3).
In the clock cycle (3), the type of the bus cycle is set to be the sequential cycle (Seq), and the CPU 10 generates an address Aa+1 obtained by incrementing the address Aa in the immediately preceding bus cycle and the so generated address to the memory controller 20. In the clock cycle (5), the address Aa+1 is supplied to the memory 30 as the memory address output MADDR from the memory controller 20, and then read data Da+1 corresponding to the address Aa+1 is supplied to the memory controller 20 as the data MDIN from the memory 30.
In the clock cycle (5), the type of the bus cycle is set to the nonsequential cycle (NonSeq). An address Ab from the CPU 10 is supplied to the memory controller 20. In the clock cycle (7), the address Ab is supplied to the memory 30 as the memory address output MADDR from the memory controller 20 corresponding to the address Ab, and read data Db corresponding to the address Ab is supplied from the memory 30 to the memory controller 20 as the data MDIN. The types of the bus cycles are set to the nonsequential cycles (NonSeq) in the following clock cycles (9) and (11) as well.
Patent Document 1 proposes a configuration as shown in FIG. 5 as a memory controller (also termed as memory control device) for reducing an idle address state and implementing effective data transfer. Referring to FIG. 5, this memory controller includes an address counter 52 for generating a look-ahead address, an address comparator 53 for comparing an address CTADR counted up by the address counter 52 with a request address RQADR, a counter memory controller 54 for controlling the address counter 52 and the address comparator 53, and an address select driver 55 for making a selection between a count address and a request address and outputting an address B2ADR for a memory to a bus 6. Until a processor issues a next request, data at a next sequential memory address is prior read, thereby reducing the unnecessary address state and effecting improvement in performance of accessing the memory. Referring to FIG. 5, reference numeral 51 denotes a request buffer for buffering a request B1ADR from a bus 3, reference numeral 56 denotes a response buffer for receiving response data B2DATA from the bus 6, and reference numeral 57 denotes a response driver for inputting response data RSDATA and outputting response data B1DATA to the bus 3. FIG. 6 shows a timing chart described in Patent Document 1.
As shown in FIG. 6, after the memory controller in FIG. 5 has detected a continuous mode command (CRD) as a command B2CMD from a processor, the memory controller switches the address output B2ADR for the memory to an output of the address counter 52, for output.
Further, when data B2DATA output from the memory is taken in by the memory controller, erroneous data EE prior read is not latched by the response buffer (RSBF) 56, thereby invalidating the erroneous data EE.
When transition from sequential access (CRD) to nonsequential access (RD) such as transition of the address B1ADR on the bus 3 from 10 C to 200 is made, it takes several clocks to output last “DD” in the sequential access (CRD) from the data B1DATA through the bus 3 and output a next address to the memory from the address B2ADR through the bus 6.
[Patent Document 1] JP Patent Kokai Publication No. JP-A-6-161868
[Non-patent Document 1] “ARM7TDMI-S(Rev4) Technical Reference Manual” by ARM Limited., pp. 69-86, Internet <ULR: http://www.arm.com/pdfs/DDI0234A—7TDMIS_R4.pdf>